FPGA Verification Engineer – UVM (Hybrid)

by NESCO Inc in

Job role overview

  • Date posted

    May 7, 2026

  • Hiring location

    Owego

Description

ASIC & FPGA Development Engineer

The selected candidate will be responsible for ASIC & FPGA development on R&D program. This engineer will have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms. Experience with COTS based control platforms and embedded processors on FPGA platforms is required.

work mode

On-site

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